The present invention relates to a test method for a semiconductor memory device.
As such a conventional semiconductor memory device, there is provided a dynamic random access memory (DRAM) device exemplified by the diagram in FIG. 2. This DRAM has a symmetrical pattern due to limitations on the circuit layout, and includes two types of sense amplifiers SAMP1', SAMP2', SAMP3', and SAMP4'. In FIG. 2, the type of sense amplifier is indicated by the facing of the letter "F". At every other intersection between the pairs of bit lines B1'-B1#', B2'-B2#', B3'-B3#', B4'-B4#' connected to sense amplifiers respectively and the word lines W1', W2', W3', W4' is provided a memory cell MC11', MC12', MC13'... MC44'. Each pair of bit lines is connected to a corresponding pair of transfer gates TR1'--TR1#', TR2'-TR2#', TR3'-TR3#', TR4'-TR4#', and pairs of transfer gates TR1'-TR2', TR1#'-TR2#', TR3'-TR4', and TR3#'-TR4#' are connected by means of data lines D1', D1#', D2', and D2#', respectively, to a comparator 100'. The on/off states of transfer gates TR1', TR1#' and TR3', TR3#' are controlled by a control signal CSEL1' and those of transfer gates TR2', TR2#' and TR4', TR4#' are controlled by a control signal CSEL2'. In all cases, the gate is ON when the control signal CSEL1' or CSEL2' is a HIGH level, and is OFF when the control signal is a LOW level.
The comparator 100' receives the signals from two pairs of bit lines connected to two of the four sense amplifiers over the data lines D1', D1#', D2', and D2#', and compares the signal carried by data line D1' with the signal carried by data line D2' and the signal carried by data lines D1#' with the signal carried by data line D2#' to determine data matching. To test the operation of this DRAM, an identical datum (HIGH) is written to and stored in the two memory cells connected to the sense amplifiers with identical layout patterns, e.g., memory cells MC11' and MC31' connected to SAMP1' and SAMP3', respectively. A word line W1' is then made on, communicating memory cells MC11', MC31' to the respective bit lines B1', B3', thus creating potential differences between each pair of bit lines B1'-B1#' and B3'-B3#', respectively. These potential differences are amplified by sense amplifiers SAMP1' and SAMP3'.
If sense amplifiers SAMP1' and SAMP3' are functioning normally, bit lines B1', B3' will both become HIGH according to the datum HIGH written to the memory cells MC11' and MC31', and the bit lines B1#', B3#' will both be LOW. Furthermore, by setting the control signal CSEL1' HIGH when the control signal CSEL2' is LOW (i.e., transfer gates TR2', TR2#', TR4', TR4#' are OFF), the transfer gates TR1', TR1#', TR3', and TR3#' become ON, and the two pairs of bit lines B1', B1#' and B3', B3#' are communicated to data lines D1', D1#', D2', D2#'. The levels of bit lines B1', B1#' and B3', B3#' are then compared via the respective data lines by the comparator 100'. Normal operation is determined when the levels of bit lines B1' and B3', and B1#' and B3#' match, and abnormal operation is determined at all other times. Thus, two memory cells are read simultaneously and their states are compared in an operation test. Known as a multiple bit test method, this test method can be used to greatly reduce the required testing time for large capacity DRAM devices.
However, a completely symmetrical layout pattern cannot be drawn for two inputs to each of the sense amplifiers SAMP1', SAMP2', SAMP3', SAMP4' above. As a result, there is a tendency to amplify so that one of the bit lines is constantly HIGH and the other is LOW due to the asymmetrical nature of the layout pattern regardless of whether one of the bit lines in one pair is a high potential or low potential (hereinafter the potential high-low relationship) when the potential difference before amplification is small in a pair of bit lines connected to each of the sense amplifiers SAMP1' to SAMP4'. For example, this tendency appears when the potential level of the ON word line W1' is low, or when the accumulation charges in the memory cells communicated to bit lines B1', B3' are low. Furthermore, when this tendency appears, a correlative phenomenon in which the potential high-low relationship of a pair of bit lines reverses before and after amplification (hereinafter erroneous operation) sometimes appears.
Because two sense amplifiers with the same layout pattern, e.g., SAMP1' and SAMP3', are operated simultaneously and the potential high-low relationship of two pairs of bit lines connected to those sense amplifiers SAMP1' and SAMP3', i.e., B1', B1#' and B3', B3#' in this example, is compared in the conventional multiple bit test method described above, when the aforementioned erroneous operation occurs, the potential high-low relationships in each pair match because there is a tendency to amplify in the same direction in this erroneous operation. For example, if the bit lines B1' and B3' have a (slightly) higher potential than the bit lines B1#' and B3#', respectively, before amplification, and both sense amplifiers SAMP1' and SAMP3' operate erroneously with a tendency to amplify in the same direction, the bit lines B1#' and B3#' will be HIGH and the bit lines B1' and B3' will be LOW after amplification, and the potential high-low relationships of the two pairs of bit lines B1', B1#' and B3', B3#' will match. Because the levels of the data lines D1', D2' and D1#', D2#' are respectively HIGH and LOW at this time, the comparator 100' is unable to detect this erroneous operation. Thus, the conventional multiple bit test method described above cannot be applied to a so-called margin test wherein the power supply voltage Vcc is sequentially decreased from HIGH to LOW to test for normal operation.